基于RK3568核心板，GMAC0 通信异常

user11596 · January 11, 2023, 3:53am

固件类型：自行编译的固件
SDK包名称：rk356x_linux_release_v1.2.0_202111019_split_dir
SDK修改内容：修改了硬件相关的配置，关于网口相关的没有改动
Log日志：系统启动日志.txt

调测问题：有两路数据收发通讯正常，有一路网卡ping通讯正常，但是数据传输异常？网卡芯片型号：RTL8211FI

通过使用Iperf3工具，测试发现通讯异常的网卡无法向外发送数据，接收数据显示千兆速率。主控SOC使用RK3568.

测试异常网卡说明如下：
测试设备IP:192.168.1.3 测试主机IP:192.168.1.126

测试日志见附件图片。

RTL8211FI原理图见附件
请帮忙分析一下问题原因，谢谢
tchip_askquestions
系统启动日志.txt (74.7 KB)

rtl8211fi_reuse.pdf (116 KB)
3568core _ 3568_core.pdf (94.5 KB)

dengkx · January 12, 2023, 1:09am

更新最新的sdk，这个问题已经修复

dengkx · January 12, 2023, 1:19am

或者使用这两个补丁:
$ cat 0001-arm64-dts-itx-3568q-RGMII-Crystal-25M-for-PHY-PLL-ou.patch
From 8d0b614f682f48c2b27a32b5102bfcf38eda20d6 Mon Sep 17 00:00:00 2001
From: dengkx <dkx@t-chip.com.cn>
Date: Thu, 15 Sep 2022 09:37:06 +0800
Subject: [PATCH] arm64: dts: itx-3568q: RGMII Crystal 25M for PHY, PLL output
125M for TX_CLK

…/rockchip/rk3568-firefly-itx-3568q.dtsi | 30 ++++++++++++++++±-
1 file changed, 27 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-firefly-itx-3568q.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-firefly-itx-3568q.dtsi
index fc39c42d348d..219fd27fa16f 100644
— a/arch/arm64/boot/dts/rockchip/rk3568-firefly-itx-3568q.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568-firefly-itx-3568q.dtsi
@@ -281,10 +281,22 @@

&gmac0 {
status = “okay”;

tx_delay = <0x47>;
rx_delay = <0x31>;

tx_delay = <0x44>;
rx_delay = <0x35>;
snps,reset-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>;
-// snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
clock_in_out = “output”;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-rates = <0>, <125000000>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
pinctrl-names = “default”;
pinctrl-0 = <&gmac0_miim
```
       &gmac0_tx_bus2
```
```
       &gmac0_rx_bus2
```
```
       &gmac0_rgmii_clk
```
```
       &gmac0_rgmii_bus>;
```

};

&gmac1 {
@@ -292,6 +304,18 @@
tx_delay = <0x4d>;
rx_delay = <0x2d>;
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
+

clock_in_out = “output”;
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-rates = <0>, <125000000>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
pinctrl-names = “default”;
pinctrl-0 = <&gmac1m1_miim
```
       &gmac1m1_tx_bus2
```
```
       &gmac1m1_rx_bus2
```
```
       &gmac1m1_rgmii_clk
```
```
       &gmac1m1_rgmii_bus>;
```

};

&rgmii_phy0 {

2.17.1

$ cat 0002-dts-itx-3568q-gmac0-increases-the-IO-drive-capabilit.patch
From b89f257e844d9c11b2bbb71ba47f5163e9e1a4e9 Mon Sep 17 00:00:00 2001
From: dengkx <dkx@t-chip.com.cn>
Date: Tue, 11 Oct 2022 14:57:43 +0800
Subject: [PATCH] dts: itx-3568q: gmac0 increases the IO drive capability of
the CLK and TX

…/rockchip/rk3568-firefly-itx-3568q.dtsi | 37 +++++++++++++++++±
1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-firefly-itx-3568q.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-firefly-itx-3568q.dtsi
index 219fd27fa16f..8cbd991dfdcc 100644
— a/arch/arm64/boot/dts/rockchip/rk3568-firefly-itx-3568q.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568-firefly-itx-3568q.dtsi
@@ -281,7 +281,7 @@

&gmac0 {
status = “okay”;

tx_delay = <0x44>;

tx_delay = <0x4a>;
rx_delay = <0x35>;
snps,reset-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>;

@@ -404,6 +404,41 @@
};
};

gmac0 {
```
  /omit-if-no-ref/
```
```
  gmac0_tx_bus2: gmac0-tx-bus2 {
```
```
  	rockchip,pins =
```
```
  		/* gmac0_txd0 */
```

  		<2 RK_PB3 1 &pcfg_pull_none_drv_level_5>,

```
  		/* gmac0_txd1 */
```

  		<2 RK_PB4 1 &pcfg_pull_none_drv_level_5>,

```
  		/* gmac0_txen */
```
```
  		<2 RK_PB5 1 &pcfg_pull_none>;
```
```
  };
```
```
  /omit-if-no-ref/
```
```
  gmac0_rgmii_clk: gmac0-rgmii-clk {
```
```
  	rockchip,pins =
```
```
  		/* gmac0_rxclk */
```
```
  		<2 RK_PA5 2 &pcfg_pull_none>,
```
```
  		/* gmac0_txclk */
```

  		<2 RK_PB0 2 &pcfg_pull_none_drv_level_5>;

```
  };
```
```
  /omit-if-no-ref/
```
```
  gmac0_rgmii_bus: gmac0-rgmii-bus {
```
```
  	rockchip,pins =
```
```
  		/* gmac0_rxd2 */
```
```
  		<2 RK_PA3 2 &pcfg_pull_none>,
```
```
  		/* gmac0_rxd3 */
```
```
  		<2 RK_PA4 2 &pcfg_pull_none>,
```
```
  		/* gmac0_txd2 */
```

  		<2 RK_PA6 2 &pcfg_pull_none_drv_level_5>,

```
  		/* gmac0_txd3 */
```

  		<2 RK_PA7 2 &pcfg_pull_none_drv_level_5>;

```
  };
```
};

// touchscreen {
// tp_power_en: tp-power-en {
// rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;

2.17.1

基于RK3568核心板，GMAC0 通信异常

&rgmii_phy0 {

// touchscreen { // tp_power_en: tp-power-en { // rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;

// touchscreen {
// tp_power_en: tp-power-en {
// rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;