Questions about the 8ch I2S/PCM RK3288 peripheral

Chip Platform Rockchip
1

Hello,

I have some questions regarding the 8ch I2s/PCM peripheral inside the RK3288 SoC (chapter 16 of the manual).

Q1: looking at the timing diagrams starting on page 752 (sections 16.3.1 to 16.3.7), it seems that I2S allows 1 stereo channel only per output, while the DSP/PCM mode allows from 1 to 4 stereo channels on a single output (SDO0). Is it right?

Q2: the peripheral control registers list shows only 1 transmit fifo data register (I2S_TXDR on page 765). How is this unique TX data register connected to the 4 TX FIFOs?

Q3: for that matter what I understand is that the I2S_TXCR::CSR field (page 756) sets the number of stereo channels AND the number of used TX FIFOs. In PCM mode the n FIFOS can be seen as a single FIFO with a depth equal to 32 x n. Is it right?

Q4: in I2S mode, each FIFO is routed to the corresponding I2S_SDOx output. Is it right?

Q5: from the ES8323 codec data sheet it seems that this codec manages only a single stereo stream, wether configured as an I2S or a PCM device. So this would mean that it is not possible to send more than 2 channels when using the firefly board as is. Is it right?

Thanks.

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