RK3568 PCIe Entry L1.1 and L1.2

Chip Platform Rockchip
1

Hi Sirs,
In Linux Kernel driver, the driver don’t support PCIe L1.1 and L1.2.
Could you please provide the sample code?
And I have check the TRM, the L1sub Status FSM don’t have any description about the status.
Please provide the details register description.
Thanks

2

In the Chapter 18 PCIe Controller of Rockchip RK3568 TRM Part2 V1.1-20210301.pdf, all the descriptions of PCIe are already available.

Maybe you need to look at these entries: PCIE_CLIENT_POWER_CON, PCIE_CLIENT_POWER_STATUS.

https://en.t-firefly.com/doc/download/89.html#other_370

3

时间的蝴蝶 Posted at 11/22/2021 10:38
In the Chapter 18 PCIe Controller of Rockchip RK3568 TRM Part2 V1.1-20210301.pdf, all the descri …

Hi Sirs,
I have check the TRM. And Enable The RC and DUT L1.2.
And check the l1sub status, the status is 3.
[0x0300] 0x00230313 CLIENT_LTSSM_STATUS
[22:20] [ RW] pm_current_data_rate = 0x2
[ 17] [ RW] rdlh_link_up = 0x1
[ 16] [ RW] smlh_link_up = 0x1
[10:08] [ RW] l1sub_state = 0x3
[05:00] [ RW] smlh_ltssm_state = 0x13

[0x0014] 0x00000133 CLIENT_INTR_STATUS_PMC
[ 8] [ W1C] pm_dstate_update_int = 0x1
[ 7] [ W1C] linkst_out_l0s_int = 0x0
[ 6] [ RO] linkst_out_l2_int = 0x0
[ 5] [ W1C] linkst_out_l1_int = 0x1
[ 4] [ W1C] linkst_out_l1sub_int = 0x1
[ 3] [ W1C] linkst_in_l0s_int = 0x0
[ 2] [ W1C] linkst_in_l2_int = 0x0
[ 1] [ W1C] linkst_in_l1_int = 0x1
[ 0] [ W1C] linkst_in_l1sub_int = 0x1

[0x002c] 0x00000008 CLIENT_POWER_CON
[31:16] [ WO] write_enable = 0x0
[ 13] [ W1C] clk_req_n_con = 0x0
[ 12] [ W1C] clk_req_n_bypass = 0x0
[11:10] [ RW] p2_cpm_disable = 0x0
[ 9] [ RW] app_clk_pm_en = 0x0
[ 8] [ RW] sys_aux_pwr_det = 0x0
[ 6] [ RW] app_l1sub_disable = 0x0
[ 5] [ RW] app_xfer_pending = 0x0
[ 4] [ RW] app_req_exit_l1 = 0x0
[ 3] [ RW] app_ready_entr_l23 = 0x1
[ 2] [ RW] app_req_entr_l1 = 0x0
[ 1] [ RW] app_pm_xmt_pme = 0x0
[ 0] [ RW] app_clk_req_n = 0x0

I have try to set the clkreq to bypass mode. And set the clkreq to tri-state. But the l1sub status is not correct.

Please help to provide the way to configure the PCIe ASPM.
Thanks,

4

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